TSMC Chairman Dr. Mark Liu confirmed that the company’s next-generation 3nm chip manufacturing node is progressing as planned. As a world-renowned chip foundry manufacturer, TSMC is currently building a 3nm production line and is expected to switch to trial production next year. Compared with the 5nm process node, 3nm can provide almost double the logic density, supplemented by 11% performance improvement, or 27% energy efficiency improvement.
Example of gain of 3nm compared to 5nm process (picture via WCCFTech)
The statement made by TSMC executives during the previous International Solid-State Circuit Conference (ISSCC) speech confirmed the company’s confidence in the next generation of manufacturing technology.
While meeting the increasing demand for current and future products, even if the demand for products in the automotive field increases, it will not have much impact on overall production capacity.
It should be pointed out that some media have misunderstood the so-called “3nm process ahead.” After all, during the 27-minute speech on “Unleashing the Innovative Future”, the executives did not say it bluntly, and only “simply mentioned” the progress of 3nm development at the beginning and end.
In order to increase the logic density, it is necessary to carry out collaborative optimization of related technologies, which also increases a certain cost.
In addition to revealing that the development of 3nm technology is advancing as scheduled and quite smooth, Liu Deyin also provided the latest data on the 3nm process and his views on process development.
He pointed out that so far, TSMC has shipped about 1.8 billion chips based on the 7nm process node. As of 2020, the company has been a leader in the industry.
Thanks to extreme ultraviolet lithography (EUV) technology, TSMC can achieve higher fidelity, shorten cycle times, and reduce process complexity and defect rates.
It is worth mentioning that TSMC used EUV technology (including wire cutting, contact, and metal line patterning) in the ten-layer mask process at the 5nm node, and replaced the early multi-layer deep ultraviolet (DUV) process with a single-layer EUV .
Later, Liu Deyin emphasized the collaborative optimization (DTC) of design technology and the importance of the program to chip manufacturing in the past few years. For chip manufacturers, this allows them to use both design and manufacturing techniques to meet performance requirements.
In addition, DTCO allows TSMC to surpass the inherent scaling indicators when measuring the logic density of nodes, such as contact gate spacing and minimum metal spacing.
Combined with the characteristics of gate contact, single diffusion interruption, and fin reduction on the active area, it can also bring 1.8 times the logic density of 5nm to the 3nm process node.
Finally, Liu Deyin disclosed the company’s future plans, including the development of sub-3D materials and wafer-level monocrystalline hexagonal boron nitride.
The feature of both is that they can be transferred to any substrate at a lower manufacturing temperature, thus opening up a new path for manufacturing active logic layers and storage layers in three dimensions.
In addition, TSMC’s research on low-dimensional materials includes one-dimensional carbon nanotubes. The key to using this crystal channel is to develop a transistor dielectric material with a shorter gate length.
As shown in the figure above, research has shown that this technology is possible. New materials with high-k gate stacking capabilities are very suitable for manufacturing transistors with a gate length of 10nm.
Of course, in order to achieve such ambitious goals, TSMC also needs to work closely with all peers in the chip industry to ensure that the 3nm process can be developed to twice the current performance.
Taking into account that the company’s mass production of 5nm conforms to this trend, the upcoming 3nm node is also expected to follow this schedule.