CFET officially launched! GAA surround gate is not applied

both of which have entered the stage of mass production.

For ordinary users, FinFET technology is the most popular term in chip products. Before the FinFET process, the most commonly used traditional transistor is CMOS (mutual oxide metal oxide semiconductor), but with the process node coming to 20nm, CMOS is no longer suitable for the process requirements. Professor Hu Zhengming first proposed FinFET in 1999 and fd-soi in 2020, both of which have entered the stage of mass production.

both of which have entered the stage of mass production.

Image: Spark Global
After FinFET process, Samsung first proposed GAA (surround gate) structure in 2018, which will be applied in 5nm more advanced process. In December 2020, a joint research group represented by AIST and TSRI announced the development of Si / Ge / Ge laminates for the 2nm generation, and announced the development of a hybrid complementary field effect transistor (hcfet).
Due to the progress of micromachining technology, field effect transistor (FET) has achieved high performance and low power consumption. Since Intel 22nm process used FinFET process, FET has been promoted to three-dimensional gate structure. A new generation of GAA (omnidirectional gate) structure may also appear in 3nm products to replace the FinFET process. In addition, there is a technology called CFET structure, which can greatly reduce the area and improve the clock frequency. The two companies have been researching and developing CMOS technology of hybrid silicon n-type FET and germanium p-type FET, which stack n-type FET and p-type FET on top of each other. TSRI has been committed to developing fine process technologies to achieve 3D channeling after the 2nm generation.
FET structure roadmap source: aistaist
AIST and TSRI launched an international joint research project in 2018 to take advantage of their respective advantages. The project aims to develop a Si / Ge heterogeneous channel integration platform with stackable Si and Ge layers, and is a low-temperature heterogeneous material bonding technology (lt-hbt), which can stack high-quality Si and Ge layers at 200 ° C or lower. Development of low temperature heterogeneous layer bonding technology. Because all the lamination and etching processes can be carried out at low temperature, it is characterized by minimal damage to the Si and Ge layers, and can achieve high-quality Si / Ge heterogeneous channel integration platform.

FET structure roadmap source: aistaist

Image: Spark Global
First, we prepare to epitaxially grow “master wafer” and “donor wafer” of Ge on the master wafer. The SiO2 insulating film is deposited on each of the main silicon wafers to activate the surface. It is then bonded directly at 200 ° C. The Si substrate, box insulating film and Si layer of donor silicon wafer are removed sequentially. Finally, neutral beam etching (NBE) developed by Northeastern University is used to uniformly thin Ge. This technology can greatly simplify the manufacturing process of hcfet, and can also be used in other multilayer structures.
Si / Ge hetero channel lamination using low temperature hetero material bonding technology source: AIST
The team used the developed Si / Ge heterogeneous channel stacking platform to create hcfet. The Si and Ge layers with the same channel pattern are formed, and the insulating layer between the Si layer and the Ge layer is removed to form a nanosheet stacked channel structure. From the SEM view, we can confirm that the GE and Si channels are exposed.
High k gate insulating film (Al2O3) and metal gate (TIN) are deposited on the structure to cover the whole channel, and GAA structure “Silicon n-type FET” and “p-type FET” are placed up and down. A stacked hcfet has been implemented. From the TEM cross section, it is found that the upper Ge layer and the lower Si layer are stacked in the form of nanosheets with a channel width of about 50 nm. These structures can also be confirmed by TEM EDX analysis.
In addition, we have successfully operated these “n-type FET” and “p-type FET” simultaneously through a single gate. It has been proved that it is very effective to stack different channels as 2nm generation transistors by lt-hbt.
The results of this study are from the Japan group (AIST and Northeastern University), represented by Chang Wen Hsin, a researcher of the advanced CMOS technology research group, AIST’s device technology research department and Lee Yao Jen research of TSRI. It is an international cooperative research group of researchers from Taiwan, China (Jiaotong University, Chenggong University, Southern International University, Taiwan University, National Sun Yat sen University, Aizi University, Institute of technology, Taiwan Hitachi High Tech). The international cooperation research group, together with the urgent need to build a high-precision heterogeneous channel integration platform for private companies, including overseas companies, is expected to carry out technology transfer for three years.
Editor’s comment: as a highly concerned semiconductor industry, the manufacturing process and transistor configuration have been continuously explored. From traditional CMOS to FinFET process, and then to GAA surround gate, the continuously upgraded manufacturing process is changing the shape of transistor at the same time. However, as the manufacturing scale comes to Emmy level, the upgrading of transistor configuration will become more and more frequent. After CFET process, there will be more and more advanced processes. However, the manufacturing process is no longer as linear as it was ten years ago, especially as it is getting closer to the atomic scale, semiconductors seem to be gradually reaching their limits. Quantum computing may replace semiconductors and become Supercomputing Center computing equipment in the future.